初级版图设计师Junior Layout Designer

lightelligence

Junior Layout Designer

What You’ll do at Lightelligence:
• Custom layout designer to work with analog design engineers to perform layout for high speed, high performance analog/mixed signal IP blocks
• Perform DRC/LVS debug and verification for the IP blocks and help with their integration into the SOC

Preferred Qualifications:
• Experience in high performance analog layout in advanced CMOS process (28nm or smaller geometry CMOS, deep metal stack, high frequency design >1 GHz)
• Experience with layout of high-performance analog IP blocks such as PLL, DLL, SERDES, ADC, DAC, Amplifier, etc. highly desired
• Knowledge with industry standard EDA tools such as Cadence Virtuoso; experience with DRC, LVS tools and debug verification process
• Knowledge of high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices
• Strong communicator, works well independently and in team situations

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