高级版图设计师Senior Layout Designer

Senior Layout Designer

Role Description:
1. Senior layout designer to work with analog design engineers to perform layout for high speed, high performance analog/mixed signal circuits (TIA, DAC/ADC, etc.) at the block and full chip level in advanced Foundry CMOS process
2. Work closely with design lead and physical designers for top level floor planning and integration of analog IPs with the SOC system
3. Establish the layout procedures and best practices within the company while helping to build up the layout team

 

Preferred Qualifications:
1. 5+ years’ experience in high performance analog layout in advanced CMOS process (28nm or smaller geometry CMOS, deep metal stack, high frequency design >1 GHz)
2. Experience with layout of high-performance analog IP blocks such as TIA, DAC/ADC, etc. highly desired
3. Thorough knowledge with industry standard EDA tools such as Cadence Virtuoso; extensive experience with DRC, LVS tools and debug verification process
4. Experience with floor planning, block level routing and top level chip assembly
5. Knowledge of high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices
6. Experienced in robust power/signal routing and EM analysis

 

 

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