Senior DV Engineer

 

Senior DV Engineer

Role Description:
1. Build and lead a small local DV team to develop verification collateral suitable for a variety of design implementations ranging from FPGAs to ASICs
2. Drive DV tasks such as test planning and execution, coverage for digital and mixed-signal blocks
3. Construct and execute test plans and perform coverage analysis
4. Work closely and collaboratively with RTL and analog designers
5. Work with US DV team to maintain and contribute to DV methodology and best practices

Preferred Qualifications:
1. BS or greater in a relevant discipline such as Computer Science, Electrical Engineering, or Computer Engineering with at least 5-7 years of relevant work experience
2. Logic simulation skills including testbench design, stimulus generation, coverage closure, equivalence-checking and debug
3. Proficiency in UVM/VMM/eRM and a hardware description language such as SystemVerilog
4. Strong software skills (C, C++, Python) to develop and support infrastructure and flows
5. Experience with formal verification a plus
6. Experience with mixed-signal simulation and/or modeling a plus
7. Basic knowledge of Deep Neural Networks and Artificial Intelligence a plus
8.
English Fluency: High

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