Senior PD Engineer
1. Build and lead a small local team for ASIC Physical Design
2. Create high performance, high frequency digital and mixed signal designs and drive from synthesis to tapeout.
3. Responsible for feasibility analysis, wiring studies, floor-planning, chip assembly, synthesis, place & route, integrating custom/analog blocks, timing, power analysis, design signoff and GDS release.
4. Work with the Boston Physical Design team to contribute to the development of a robust place and route flow/methodology that handles the challenges of power grid infrastructure, design floorplanning, Clock and Signal Routing, STA analysis and closure, and backend design verification.
5. Work with team members across all disciplines to optimize all physical aspects of the design.
1. BS or MS in a relevant discipline such as Electrical Engineering and at least 5-7 years experience
2. Experience in P&R and Physical Design deep sub-micron technologies, at 1GHz or higher clock frequencies
3. Track record of successful tapeouts of ASICs of significant scope (technology node, die size, frequency, power)
4. Experience with SoC challenges such as multiple clock, multiple power domains is a plus.
5. Excited to work in an energetic environment with a talented and enthusiastic team!
6. English fluency: high