RTL Design Engineer
- Perform block-level and SoC-level micro-architecture design, documentation and RTL coding
- Datapath, control and chip-global features such as power management, clock-domain-crossings, reset, initialization, and DFx (Design for Test, Debug, Manufacturing, Yield, etc)
- Collaborate with other members of the design and verification teams as well as other disciplines in the company.
- BS or MS in a relevant discipline such as Electrical Engineering and at least 3-5 years experience
- Experience delivering RTL modules in Verilog and System Verilog
- Scripting and experience with industry-standard design automation tools
- Experience with industry standard EDA tools
- Track record of successful tapeouts of ASICs of significant scope (size, frequency, power)
- Basic knowledge of Deep Neural Networks and Artificial Intelligence a plus
- Willingness to learn new skills and do the work necessary to succeed.
- Business-level fluency in English