IC Substrate Designer is a technical position that can design multiple complex laminate substrates to meet various products’ requirements. The candidate will work with IC designers and PCB system integration designers to find ways to optimize the overall package and substrate design and tape-out. This position offers the opportunity to work across multiple organizations such as IC design team, physic design team, PCB team, laminate suppliers and packaging & assembly suppliers.
- Mechanical test vehicle design, to support product qualification
- SIP substrate Layout design and tape out.
- Skills in Cadence SiP software and layout Symbol Generation/validation.
- Good knowledge base in the areas of signal integrity and power integrity.
- Familiar laminate substrate processes, stack-up, design rules and laminate supplier chain
- Coordinating DRC review with suppliers and making sure of design for manufacture
- Generating and maintain product mechanical documentation/application note;
- Responsible for establishing a commitment to team work and customers
- Bachelor’s Degree in EE/ME engineering or equivalent of education and experience.
- A minimum of 5 years of relevant semiconductor packaging substrate design experience.
- Experience using Cadence SiP package design tools is required, wafer level package design is a plus.
- Signal Integrity / Power Integrity (SI/PI) experience is a plus.
- Experience in programming language(C/C++) or scripting language is a plus.
- Good speaking English and communication skills are required.
- Self-motivated and team oriented with the ability to meet aggressive schedules.
- Demonstrated ability to efficiently complete tasks with minimal supervision.
- Must be very detail oriented, organized and able to work well in a team environment.